The present invention relates generally to semiconductor devices and more particularly to methods for forming shallow trench isolation structures with rounded lower trench corners in the manufacture of semiconductor devices.
In the fabrication of semiconductor devices, isolation structures are formed between active areas in which electrical devices such as transistors, memory cells, or the like, are to be formed. The isolation structures are typically formed during initial processing of a semiconductor substrate, prior to the formation of such electrical devices. Typical isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) processes, by which isolation structures are formed between active regions of a semiconductor device. As semiconductor device dimensions have been reduced over the past several years, limitations on the scalability of and other problems associated with LOCOS isolation techniques, have resulted in a general trend away from LOCOS techniques and an increase in the use of STI techniques, particular in modem, high device density applications.
STI isolation techniques involve the formation of shallow trenches in the isolation areas or regions of a semiconductor wafer, which are subsequently filled with dielectric material such as silicon dioxide (SiO2) to provide electrical isolation between devices subsequently formed in the active regions on either side of the filled trenches. A pad oxide layer and a nitride layer are typically formed over the substrate surface and patterned to expose only the isolation regions, with the prospective active device regions covered. The nitride layer operates as a hard mask during subsequent processing steps, and the pad oxide layer functions to relieve stress between the underlying silicon substrate and the nitride layer. An anisotropic (e.g., xe2x80x9cdryxe2x80x9d) etch is then performed to form a trench through the nitride, pad oxide, and substrate. Once the trench is etched, dielectric material is deposited to fill the trench with oxide. Thereafter, the device is commonly planarized using a chemical mechanical polishing (CMP) process and the nitride protection layer is removed.
A conventional STI process is illustrated in FIGS. 1-7 to form trench isolation structures in a semiconductor device 12. In FIG. 1, a thermal oxidation process is used to grow a pad oxide layer 14 over a semiconductor substrate 16. A nitride layer 18, such as Si3N4 is then deposited in FIG. 2, such as by low pressure chemical vapor deposition (LPCVD). The nitride layer 18 is used to protect the active regions of the substrate 16 from adverse effects of the subsequent formation of isolation trenches between the active regions. The active regions of the device 12 are then masked in FIG. 3 using a patterned etch mask 20, leaving the isolation region of the nitride layer 18 exposed. A dry etch 22 is performed to form a trench 24 through the nitride layer 18, the pad oxide layer 14, and into the substrate 16. The active mask 20 is then removed in FIG. 4 and an oxide liner 26 is formed in the trench 24 to remove or repair substrate damage caused by the trench etch process 22.
Once the trench 24 and the liner 26 are formed, a dielectric material 28 is deposited in FIG. 5 via a deposition process 30 to fill the trench 24 and also to cover the nitride layer 18 in the active regions of the device 12. In FIG. 6, a chemical mechanical polishing (CMP) process 32 is used to planarize the upper surface of the device 12, which exposes the remainder of the nitride layer 18. Following planarization, the nitride layer 18 is removed via an etch process 34 in FIG. 7 to complete the isolation process. However, in conventional isolation processing, sharp corners in the isolation trench can cause various problems with the operation performance of transistors and other devices fabricated in the adjacent active regions of the device 12. In particular, the sharp lower trench corners 36 in FIG. 7 have been found to create stresses in the substrate material 16 proximate the trench 24.
Such stresses can lead to carrier mobility degradation with corresponding worsening of performance parameters (e.g., drive current capability, increased threshold voltage, etc.) in devices such as field effect transistors subsequently formed in the active regions of the device 12. In addition, the sharp corners 36 have been found to lower the threshold voltages of parasitic transistors having channels beneath the isolation structures, and hence to worsen the parasitic leakage between transistors formed on either side thereof. Thus, there remains a need for improved STI processes and techniques by which the sharpness of lower trench corners may be decreased in order to reduce or mitigate the device performance problems associated therewith.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention provides methods for forming isolation structures and STI trenches therefor in a semiconductor device, which may be carried out in a variety of semiconductor manufacturing processes. The invention involves rounding lower corners of isolation trenches prior to trench filling with dielectric materials, so as to mitigate the adverse stresses and other deleterious effects associated with the sharp corners of conventional STI methodologies on subsequently formed electrical devices. In one aspect of the invention, a trench is formed in a semiconductor substrate having sidewalls, a bottom, and lower corners between the sidewalls and the bottom. The lower comers of the trench are then rounded prior to performing further etch processes. Thereafter, an oxide liner is formed over the exposed substrate surfaces in the trench, and the trench is filled with dielectric material to form an isolation structure in the semiconductor device.
In one example, the corner rounding is accomplished through growth of a sacrificial oxide over the sidewalls and bottom of the trench immediately after forming the trench, which is removed directly thereafter via a wet etch process. The sacrificial oxide may be formed using a thermal oxidation process which oxidizes substrate material from the sidewalls and the bottom faster than from the lower corners of the trench. As a result, the lower corners of the trench are rounded off to mitigate stresses and other problems associated with sharp lower corners of prior STI trenches, such as those mentioned above. The removal of the sacrificial oxide by subsequent wet etching exposes the rounded portions of the substrate at the lower corners of the trench. Thereafter, a final oxide liner may be formed in the trench, over the sidewalls, bottom, and rounded lower corners thereof, and a trench fill deposition process is performed to fill the trench with dielectric material to form the isolation structure.
Another aspect of the invention provides for growing a second sacrificial oxide over the sidewalls and bottom of the trench after removing the first sacrificial oxide, and removing the second sacrificial oxide immediately after growing the second sacrificial oxide using a wet etch process. As with the first sacrificial oxide, the growth of the second sacrificial oxide further rounds the lower trench corners to combat the above shortcomings of prior techniques. In this regard, a thermal oxidation may also be used for the second sacrificial oxide formation, in which substrate material oxidizes from the sidewalls and the bottom faster than from the lower corners of the trench. The growth and removal of sacrificial oxides in the trench may be repeated any number of times in accordance with the invention, thus facilitating lower corner rounding to any desired degree prior to liner formation and subsequent trench filling operations.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.